Electrically erasable programmable read only memory (EEPROM) devices can store data in a nonvolatile manner as charges on stacked gates. Two types of EEPROM devices are flash memory devices and floating gate tunnel oxide (FLOTOX) memory devices. FLOTOX type EEPROM devices can have a unit memory cell with two transistors, one of which is a selection transistor configured to address a desired cell and the other of which is a memory transistor configured to store data. Flash type EEPROM devices can have a memory cell with one transistor. A cell array in a flash memory device can be classified as a NAND-type or a NOR-type depending upon the logic configuration of the memory cells. In a NAND-type cell array, a plurality of memory cells are serially connected to form cell strings, and a plurality of cell strings are connected in parallel with one another. Similar to FLOTOX type memory devices, two selection transistors are connected to opposite ends of a cell string of the NAND-type cell array. However, selection transistors of a FLOTOX type memory device select memory cells, while selection transistors of a NAND-type cell array select a cell string.
Transistors of a typical EEPROM cell include a lower conductive layer, an insulating layer, and an upper conductive layer that are sequentially stacked. The lower conductive layer and the upper conductive layer of a memory cell are electrically insulated from one another by the insulating layer so as to enable accumulation of charge on one of the conductive layers to store data. For selection transistors and peripheral transistors, the lower conductive layer and the upper conductive layer are electrically connected. Various different structures and related methods for electrically connecting lower and upper conductive layers have been suggested, such as illustrated by the EEPROM memory devices with selection transistors disclosed in U.S. Pat. Nos. 4,780,431 and 6,221,717.
FIGS. 1 through 3 are cross-sectional views of a conventional method of fabricating a semiconductor memory device.
With reference to FIG. 1, a field oxide layer 2 is formed on a semiconductor substrate 1. A gate insulating layer 3 and a first polysilicon layer 4 are formed on the substrate 1 between the field oxide layers 2. The field oxide layer 2 defines a cell region and a peripheral region of the substrate 1. An oxide layer 5 is formed on the first polysilicon layer 4. A resist mask 6 is formed on the resultant structure and defines windows 7 and 8 that expose portions of the oxide layer 5. The insulating layer 5 is etched using the resist mask 6 to form small windows 9 and 10 exposing portions of the gate insulating layer 3.
With reference to FIG. 2, the resist mask 6 is removed. A second polysilicon layer 11 is formed on a surface of the substrate 1. A cell transistor and resist masks 12, 13, and 14 are formed on the second polysilicon layer 11.
With reference to FIG. 3, the second polysilicon layer 11, the oxide layer 5 and the first polysilicon layer 4 are sequentially patterned using the resist masks 12, 13, and 14 to respectively form a cell transistor 15, a selection transistor 16, and a gate pattern of a peripheral transistor 17.
Accordingly, by forming the small windows 9 and 10 to remove portions of the oxide layer within the selection transistor 15 and the peripheral transistor 17, the polysilicon layers 4 and 11 therein can be electrically connected to each other through the widows 9 and 10. As can be appreciated, avoiding misalignment of such windows during fabrication can limit the integration density of such devices.